Wednesday November 16, 2005

IEEE ITC 2005, Austin - Test: Survival Of The Fittest

I am back from Austin, the live music capital of the world ... country ... a whole another country within a country ;) ... and here are the tunes I heard at the International Test Conference.

SUMMARY My personal focus was on microprocessor testing. Some key take-aways were: + Our competitors and partners have multi core SoC test problems on their minds (as expected). + Confirmed that cache preload is an established methodology for SoC functional testing in the industry. + There was an expected buzz about delay fault testing and compression. + No one seems to have been successful in taking transition tests to the extent that it replaces functional testing. Functional tests continue to rule their niche; while transition tests continue to enhance their value in production. + The most interesting papers on high speed serial interfaces were from our own team(s). + (personal opinion) For my first ITC experience, the overall paper quality was below expectations.

TUTORIAL: Dealing with timing issues in sub--100nm designs Li-C. Wang,UCSB and Magdy S. Abadir, Freescale

This tutorial primarily covered two sub-areas: Statistical STA and speed binning. Semiconductor metrology, modeling and variability decomposition were presented in a consolidated effort. Related issues from process characterization to speed binning were highlighted.

SSTA refers to timing analysis engines using statistical cell delay models with distribution functions as an input, as opposed to worst case STA cell delay models. Methods for model extraction were covered. A comparative motivation for SSTA was presented that showed a refinement in delay margin compared to worst case. A DAC 05 paper reference showed an SSTA application where the error in computing the standard deviation of the delay margin was on average only 0.19% of the measured path delay; on a large microprocessor block (> 100K cells, 90nm, 492 critical paths). Inclusion methods for power noise were proposed.

For speed binning, Freescale data was presented that showed that complex (through memory) transition tests give the best correlation to functional frequencies. Miscorrelation contributors, including higher switching with TT were mentioned.

STA generated critical paths do not always correlate to post-silicon speed paths. Path delay test helps define a correlation metric. Better correlation to Fmax was achieved by targeting individual paths instead of the entire path delay test set.

SESSION 6: Microprocessor Test

6.1: Testability Features of the First -Generation CELL Processor M. Riley, L. Bushard, N. Chelstrom, S. Ferguson, IBM; N. Kiryu, Toshiba Corp.

This presentation was nothing but a list of the testability features. Yet, there were a few items of interest to denote with more details in the paper. + The processor has a high speed asynchronous interconnect to memory and system io + IO and memory clocks are used in a synchronous mode during scan test + 46% of the logic is non scannable to save area and power + partial cores are supported + Single clock scan design with Thold_b clock control + Test modes: Full Access (scan), LBIST, OPMISR, ABIST, AVP, SST (Specialized Scan), IO, Free Run + Advanced Verification Program: functional test execution by loading memory + Modes are combined for test sequences

6.2: Test Methodology for Freescale's e600 core based on PowerPC N. Tendolkar, D. Belete, A. Razdan, H. Reyes, B. Schwarz, M. Sullivan, Freescale Semiconductor

This presentation was a variant of a previous paper and was not too interesting beyond the emphasis on LBIST and at-speed scan. The methodology includes an array clock freeze mode where outputs are driven to a fixed value.

6.3 Drive only at speed functional testing DOFT: One of the techniques Intel is using to control test cost Mike Tripp, Silvio Picano, Baruch Schnarch, Intel Corp.

As the title suggests, the ATE drives the stimulus and the response is either compared to the expected response on the device-under-test (DUT), or compressed into a signature on the DUT. The output of the comparison or signature is driven out of a test port for pass / fail determination by the ATE.

DOFT enables low cost tester usage, efficient use of tester memory (by 20-50%), reduces tester turn-around time limitations, and supports multi-site testing. The ATE could also drive the expected response in addition to the stimulus, and the two could be internally compared on the DUT(s) with DUT drivers tri-stated. A Signature mode is used on Pentium M, with efforts in place to eliminate X states.

The Signature mode is also used on the 65 nm Pentium-4. A DOFT like methodology could also be leveraged with future processor architectures with multiple cores, and with high speed asynchronous serial interfaces with external loopback relays.

PANEL 6: Have we addressed challenges for SoC testing ? Moderator: S. Menon, Intel, Panel: Y. Zorian, Virage, T. Wood, AMD, N. Chelstorm IBM, Raj Raina, Freescale.

This panel discussion was the highlight for me at ITC05; the reason being that there was representation from all major SoC microprocessor companies under one roof. The discussion covered SoC and / or multi-core testing. It was obvious from the discussion that SoC testing is still a challenge for the industry. The strategy followed is to divide and conquer using structural / BIST techniques, at least for production. IEEE Std. 1500 Testability Method for Embedded Core based ICs, seemed to be widely referenced or utilized.

The Q&A revolved around the following topics: + speed guarantee testing (was relegated to systems at AMD) + partial core testing strategies + non/availability of yield predictors based on partial cores / die size. + reliability of tested good cores with defective cores on chip + true array speed determination using MBIST and related design margins for control & data paths + speed binning with the existence of asynchronous domains

There was an open call (from R. Raina) for papers and development of methodologies (beyond cache preload) that reuse SoC on-chip memory as tester memory in some form of BIST. In conclusion, there was a consensus on the fact that many problems still remain unresolved.

Other sessions attended, but lacking major points of interest to report, were: 11.1 Enhanced Launch-Off Capture Transition Fault testing 11.2 Methods for improving transition Fault Coverage Using broadside Tests 12.3 Automated Mapping Of Precomputed Module Level Test Sequences to Processor Instructions PANEL 4: Business Constraints Guide Test Decisions - Not Vice Versa 21.1 BIST for Molecular Electronics Based Nanofabrics 21.2 Defect oriented testing and Diagnosis of Digital ufluid based bio-chips 21.3 A new approach for Massive Parallel Scan Design 27.1 A comprehensive Production Solution for SATA based on AWG and Undersampling Advantest 6.5G Presentation Advantest CertiMax Demo 45.2 Programmable MBIST 45.3 Full-speed Field Programmable MBIST Controller (2005-11-16 15:16:00.0) Permalink Comments [0]