Una verita' quasi ovvia legata al fatto che i multicore rendono il calcolo parallelo (in tutte le sue forme) una realta' per le masse.
Su questo punto consiglio di leggere una intervista
molto interessante a due veri maestri, Hennessy & Patterson
(Stanford & Berkeley):
http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=445
Riguardo al necessario cambiamento dei paradigmi software,
l'articolo piu' citato forse e' questo:
The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software
http://www.gotw.ca/publications/concurrency-ddj.htm
Persino Microsoft e' d'accordo:
Software and the Concurrency Revolution
http://acmqueue.com/modules.php?name=Content&pa=showpage&pid=332&page=1
Per approfondire veramente, esiste il rapporto corposo di Berkeley
citato da Patterson:
The Landscape of Parallel Computing Research: A View from Berkeley
http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.html
http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.pdf
E inoltre si potra' seguire la presentazione dalla viva voce di Patterson:
The Stanford EE Computer Systems Colloquium (EE380) will be hosting a talk by Dave Patterson of UC Berkeley on January 31st. He is author or co-author of a number of books, including two of the primary texts on computer architecture, and will be presenting "The Berkeley View: A New Framework and a New Platform for Parallel Research." The EE380 presentations are always made available as streaming video, usually within a day of the presentation, and can be accessed through http://ee380.stanford.edu.
To view the talk, go to http://ee380.stanford.edu/ and click on the video camera icon for that presentation. You may have to register your e-mail address to get in. Previous talks from the current academic year can be accessed through links on the left, and talks from previous years can be accessed through the "Past Colloquia" link on the left.
============= From Dave Patterson's abstract: ===============
To rapidly evaluate all the possible alternatives in parallel
architectures and programming systems, we need a flexible, scalable, and
economical platform that is fast enough to run extensive applications
and operating systems.
Today, one to two dozen processor cores can be programmed into a single
FPGA. With multiple FPGAs on a board and multiple boards in a system,
1000 processor architectures can be explored. Such a system will not
just invigorate multiprocessors research in the architecture community,
but since processors cores can run at 100 to 200 MHz, a large scale
multiprocessor would be fast enough to run operating systems and large
programs at speeds sufficient to support software research. Hence, we
believe such a system will accelerate research across all the fields
that touch multiple processors: operating systems, compilers, debuggers,
programming languages, scientific libraries, and so on. Thus the acronym
RAMP, for Research Accelerator for Multiple Processors.
A group of 10 investigators from 6 universities (Berkeley, CMU, MIT,
Stanford Texas Washington) have volunteered to create th RAMP "gateware"
(logic to go into the FPGAs) and have the boards fabricated and
available at cost . It will run industrial standard instruction sets
(Power, SPARC, ...) and operating systems (Linux, Solaris, ...) We hope
to have a system that can scale to 1000 processors in late 2007 that
costs universities about $100 per processor. I'll report on our results
for the initial RAMP implementations at the meeting.Those interested
learning more should take a look at:
http://ramp.eecs.berkeley.edu/.
==================================================
As a prep for Dave Patterson's talk, it might be useful to watch the presentation by Ian Buck in the 2006-2007 Fall Quarter schedule, titled "Computing on the GPU GE Force 88000 and NVIDIA CUDA." They are doing some pretty amazing things with this card and a new NVIDIA C-compiler that simplifies writing general processing programs for this GPU.
Quest'ultimo punto in relazione a quanto si puo' fare con gli acceleratori (siano essi GPU come NVIDIA o ATI/AMD utilizzati in modalità GPGPU, Cell di IBM/Sony o Clearspeed).
