Thursday I attended a High Computing Seminar at the Danish Technical University (DTU). Ruud van der Pas, Sun Microsystems was on his annual visit in Denmark and gave a talk on Throughput Performance on the UltraSPARC T2 processor, based on the notion "core equivalent".
If you havn't heard it - there's a new kid on the block after the Niagara 2 chip, and thats Victoria Falls - a 2-way T2+ chip - and this is a work horse! The more work you throw at it, the better it performs. Where the Niagara T2 chip has 8 processor cores each with 8 threads and each core has a decent dedicated floating point unit. The Victoria falls chip has either 2 or 4 chips, with 8 cores per chip, 128 or 256 threads in all. Also the 8 L2 cache banks has been freed up, to allow faster memory access.
Chip Multi Threading (CMT) is a technology that allows multiple threads (process) to simultaneously share a single computing resource, such as a core. This greatly increases the efficiency of usage of the core. At the same time, multiple cores share chip resources, such as memory controllers and caches, thereby improving their utilization. The result is unprecedented per-chip performance.
This is a really good video with David Patterson from UC Berkeley giving his views on the Niagara 2 chip performance. You propably recognize the name - he is the co-author of one of the best machine architecture books written to date. Patterson and Hennessy even based the "putting it all together chapter" of their book on the Niagara chip.