Durgam Vahia's Weblog: OpenSPARC - Open-source Multi-core, Multi-thread Processor Design

Interesting analysis on open-source hardware, from one of the most respected national newspapers in India. Touches many policy making as well as business model related topics, relating to the impact of open-source, in the developing economies. Having been involved with institutions in India, Europe, China, Brazil, it is quite apparent that open-source brings unique benefits to these nations in jump-starting industries where traditional barriers to entry are quite high.

Incidentally, I just reviewed couple of Masters' level theses on microprocessor design and verification using open-source hardware in one of the Indian universities. Needless to say, they used state-of-the-art chip multi-threading (CMT) technology - OpenSPARC - for their research. Additionally, on graduation, these students are expected to teach in another Engineering institution, multiplying the skill base.

Some argue that macro-economic and policy decisions are too far removed from the ground realities - Not from my vantage point ..

Those following OpenSPARC ports on various FPGA platforms might have caught this recent announcement from Xilinx and BEEcube:

Xilinx & BEEcube to Unveil Next-Generation FPGA-based Multi-core SoC Development Platform for Sun OpenSPARC

The interesting part of this announcement is that BEE3 hardware platform has much larger FPGA capacity compared to the OpenSPARC Evaluation Board (also known as Xilinx XUPV5 board). Additionally, BEE3 supports up-to 64GB DDR2 DRAM, eight 10GigE interfaces, and 4 PCIe x8 communication links.

As a result, this platform allows up-to four, four-threaded, OpenSPARC T1 cores to be mapped on a single board which enables truly multi-core multi-threaded soft cores to be emulated on FPGAs. As mentioned in my previous post, a reference design with dual-core T1is currently included in the v1.7 of the OpenSPARC T1 hardware download package.

I have been working with Synopsys University Program to develop short-course series for academicians, students, and generally anyone interested in acquiring basic skills in various functional areas of hardware design or in Electronic Design Automation (EDA) tools. As part of this effort, we just launched the first short-course in Logic Synthesis.

This course uses OpenSPARC T1 IEEE-754 compliant Floating-Point Unit (FPU) and Synopsys Design Compiler to walk users through various optimizations to achieve certain timing and area objectives.

If you are part of the Synopsys University Program, you can download the course package through Synopsys SolvNet. Alternatively, you can also download it from the OpenSPARC.net.

We have more courses in the pipe-line but do feel free to send us ideas on what you would like to see.

It always feels great to see work like this .. 

http://www.srikiran.net/blog/2009/03/30/opensparc-t2-synthesis-part-1/

We are delighted to announce the availability of OpenSPARC T1 version 1.7. With this release, community can port a truly multi-core multi-thread 64bit commercial processor design on FPGAs. Additionally, we now support two different FPGA boards of different capacities. First one is OpenSPARC Evaluation Board that hosts single Xilinx XC5VLX110T device, and the second one, called BEE3,  is from a start-up company called BEEcube. BEE3 has four larger size Xilinx XC5VLX155T FPGA devices with support for up-to 64GB memory (More about BEEcube in the next blog entry).

Some of the notable features of this release are:

• Dual core T1 design with each SPARC core residing on one OpenSPARC FPGA evaluation board. Each core could be single thread or four-threaded (allows up-to 8 threads)
  
• Ability to boot Ubuntu Linux as well as OpenSolaris on single core and dual-core reference designs
  
• Support for the BEE3 board that allows up-to 4 SPARC cores to be mapped on a single board (allows up-to 16 hardware threads)

Finally, this release also supports Xilinx ISE and EDK version 10.1.

We hope this release will further enable community to build truly multi-core, multi-thread hardware platform in the configurable environment.

We are delighted to announce that University of Sao Paulo, Brazil is now the first OpenSPARC Center of Excellence in the Latin America. USP is one of the largest institutions of higher education in Brazil and boasts 75,000 enrolled students.

OpenSPARC team has been working closely with the faculty and students of Pervasive Computing and High Performance Group (PAD) and the Department of Electronic Systems Engineering  at the USP which has been actively involved in the research in the areas of reconfigurable computing, transactional cache models, and functional verification.

It's great to see multi-core related research and course-work being developed using the OpenSPARC technology in one of the top schools in Latin America.

Over the last few months, Nangate and Sun have been collaborating to get Nangate's 45nm Open Cell Library work seamlessly with the OpenSPARC T1 and T2 design. After comprehensive qualification, we are delighted to announce the availability of this solution to the hardware designers everywhere.

Since OpenSPARC package mostly consists of the HDL (verilog) of the UltraSPARC T1 and T2 processors, Nangate's offering is a critical piece in allowing users to explore back-end flows, including logic synthesis, and place and route.

As a result of this work, users can now synthesize, compose, and optimize state-of-the-art OpenSPARC T1 and OpenSPARC T2 design blocks, using industry standard synthesis tools, on a 45nm technology supplied by Nangate. We believe this combination will facilitate research and experimentation in modern VLSI design topics like timing and noise, reliability, and process variation among other things. We also believe the open-source nature of these two offerings will allow researchers to modify and test new ideas in a consistent and reproducible manner.

We are delighted to announce that the new version of OpenSPARC T2 (release 1.2) is now avialable for download from http://www.opensparc.net/opensparc-t2/version-1.2-released.html

In the 1.0 release of the OpenSPARC T2, we had to remove two critical IO interface design files - PCI-express and 10G Ethernet - to comply with the legal restrictions. To provide OpenSPARC users alternative means to simulate the entire T2 system-on-chip (SoC) functionality, Sun has developed behavioral models for these two design blocks. These models have similar functionality as the original RTL but are written in the SystemC language. This release, for the first time, allows users to simulate OpenSPARC T2 design with all the IO interfaces of the chip including PCIe and 10G Ethernet. We have also augmented the verification environment, test bench, and test vectors so that users can verify the current design as well as any new variant of it.

Since OpenSPARC T2's PCI-express functionality only supports root-complex configuration, users would need to have access to Denali PureSpec PCI-express model to exercise this model.

Finally, we added one missing piece (64-bit Vector.so library) that would allow OpenSPARC T2 simulation to run under 64-bit Linux operating system which was missing earlier. With this piece in place, T2 simulation can now be run both on 32b as well as 64b Linux platforms on x86 hardware.

 We hope this will encourage work in the areas of IO and SoC design.

What's common among these three things - Europe, Textbook and the Training Material .... Read on ..

We just announced whole bunch of new activities around OpenSPARC. We hope this will further reduce barriers to adoption for the state-of-the-art Chip Multi-threading (CMT) technology for the educators and entrepreneurs throughout the world.

Sun Microsystems and Europractice , a European Union-backed non-profit stimulation project, based in England, have signed a three-year collaboration agreement to promote OpenSPARC as a reference design among 650 universities and research institutions across 38 countries in the European region. You can read the full Europractice press release here

Sun has also just released a new book: OpenSPARC Internals, a reference resource for OpenSPARC designers, developers and programmers. We belive this will be a tremendously useful resource as a single source of information, not just as a design detail document but also as a cookbook that helps with setting up simulation and emulation environments, making changes to the OpenSPARC code, fitting the OpenSPARC RTL onto an FPGA, and more. The book was written by the OpenSPARC team of engineers, and edited by David Weaver. What's more? PDF of the book is available for free for download.

As a bonus, we have also added 12 modules (over 5 hours) of OpenSPARC online training material. This material, created by engineers who architected, designed and developed UltraSPARC T1 and T2, will provide OpenSPARC community a quick way to get started with the design and available resources.

It has been a very busy and yet exciting summer. We finally were able to deliver on a real FPGA development board for the OpenSPARC T1 design - something we have been collaborating on with our partner Xilinx Inc. for over two years. Check out the joint press release from Sun and Xilinx of the announcement of this platform Evaluation Platform here.

We also simultaneously announced the university donation program for the OpenSPARC Evaluation kit . Through this program, qualified universities throughout the world can apply for the donation of this board by submitting their academic and/or research proposal to Sun. We believe this seeding will result in significant new activity in the academic world around the state-of-the art Chip Multi-threading (CMT) technology embedded in the OpenSPARC architecture and design.

Here are some of the pointers to get started:

OpenSPARC University Program
Xilinx University Program
Digilent Inc.for directly ordering the board

We had another successful RAMP retreat on August 19th and 20th. Over the last two years of our association, we have effectively used RAMP community to drive OpenSPARC feature development and to connect with professors/industry partners.

We demonstrated and presented three topics this time (Slides from this and previous RAMP retreats are located here. Search for "OpenSPARC".)

• OpenSolaris running on OpenSPARC FPGA Development board based on Virtex5 technology by Xilinx
• Dual board reference design implementing dual-core T1 on FPGAs
• Support for Bee3 board by BeeCube - a spin-off from UC Berkeley

Few highlights from the OpenSPARC perspective:

• Thomas Thatcher and Paul Hartke did a really nice job presenting OpenSPARC updates to the RAMP community
• Fully functional 4-thread OpenSPARC T1 reference design booting OpenSolaris on a Bee3 board from Beecube
• Strong interest from many professors in acquiring OpenSPARC evaluation kit

Lot of hard work goes on behind the scene around such events to show continuing technical progress on OpenSPARC side. I would like to thank everyone involved, especially those involved in getting dual-core/board reference design functional in a very short time. This, together with the kit and the Bee3 port, we clearly showed the compelling and relevant progress to the RAMP community.

Wanted to highlight that deadline for the OpenSPARC contest is fast approaching. Submissions must be turned in by June 30th to be eligible.

I have seen many interesting questions on OpenSPARC forum on different topics including design exploration, FPGA port, design verification infrastructure, and silicon implementation, which leads me to believe that many of you are pursuing interesting lab and research work around OpenSPARC. This contest can give your work (and you, of course) a lot of visibility and a chance to win some serious money. For the students out there, this can be a significant resume booster. So do participate in the contest and turn in your work.

Looking forward to seeing thriving hardware design community.

If you have been following OpenSPARC release train, you probably noticed that Sun just open-sourced one of the critical blocks of the OpenSPARC T2 (aka Niagara2) processor - Network Interface Unit (NIU). Details of this release are here - OpenSPARC T2 Version 1.1.

NIU is an Ethernet to host interface bridge and supports up to four Ethernet ports and is designed to provide scalable, high performance packet processing, optimized for high throughput computing and networking architecture. Some of the key features of the NIU include: packet classification for load balancing, checksum CRC off loading, and channelized and locatable DMA support. For the network connectivity, supported port configurations include dual 10 Gigabit Ethernet.

OpenSPARC T2 v1.1 now also supports verification and synthesis flows on Linux running on x64 hardware platform. We hope this will significantly increase the user base of this product.

Great to see the respected magazine "The Economist" running an article on open-source hardware in its quarterly technology report - Open Sesame.

This is a clear indication that open-source hardware is still in its infancy and many opportunities exist at all levels of the pyramid to benefit from this paradigm. Students can learn from the commercial class designs, developers and customers benefit from open system architectures, interfaces and specifications, and corporations can get a better and faster pulse of the market trends.

Having open-sourced two of the crown-jewels of Sun, UltraSPARC T1 and UltraSPARC T2 microprocessors, with regular new feature introductions (8 releases over two years), Sun really understands the value of openness and great to see others catching up to the idea.

Here comes one more exciting announcement from the OpenSPARC team. We just released version 1.6 of OpenSPARC T1. You can read up the details and download the design from OpenSPARC T1 download page but here are some salient features of this release:

• You can now boot OpenSolaris on the OpenSPARC T1 core mapped on Xilinx ML505-XC5VLX110T board.
• You can choose single-thread or four-thread T1 core to build your own system. Yeah, this is truly multi-threaded hardware on the FPGAs
• You can connect the board to the network and use telnet and ftp applications

Team has been working towards this milestone for a long time and last two releases have been stepping stones towards this outcome. So we are really happy to get this out. This has also been a very effective collaboration between OpenSPARC team at Sun and the Xilinx University Program. Without the FPGA technology expertise of our Xilinx colleagues, this wouldn't have been possible.

So keep on innovating, folks!