OpenSPARC, Xilinx and BEEcube
Those following OpenSPARC ports on various FPGA platforms might have caught this recent announcement from Xilinx and BEEcube:
Xilinx & BEEcube to Unveil Next-Generation FPGA-based Multi-core SoC Development Platform for Sun OpenSPARC
The interesting part of this announcement is that BEE3 hardware platform has much larger FPGA capacity compared to the OpenSPARC Evaluation Board (also known as Xilinx XUPV5 board). Additionally, BEE3 supports up-to 64GB DDR2 DRAM, eight 10GigE interfaces, and 4 PCIe x8 communication links.
As a result, this platform allows up-to four, four-threaded, OpenSPARC T1 cores to be mapped on a single board which enables truly multi-core multi-threaded soft cores to be emulated on FPGAs. As mentioned in my previous post, a reference design with dual-core T1is currently included in the v1.7 of the OpenSPARC T1 hardware download package.
