Announcing OpenSPARC V1.7
We are delighted to announce the availability of OpenSPARC T1 version 1.7. With this release, community can port a truly multi-core multi-thread 64bit commercial processor design on FPGAs. Additionally, we now support two different FPGA boards of different capacities. First one is OpenSPARC Evaluation Board that hosts single Xilinx XC5VLX110T device, and the second one, called BEE3, is from a start-up company called BEEcube. BEE3 has four larger size Xilinx XC5VLX155T FPGA devices with support for up-to 64GB memory (More about BEEcube in the next blog entry).
Some of the notable features of this release are:
- Dual core T1 design with each SPARC core residing on one OpenSPARC FPGA
evaluation board. Each core could be single thread or four-threaded (allows up-to
8 threads)
- Ability to boot Ubuntu Linux as well as OpenSolaris on single
core and dual-core reference designs
- Support for the BEE3 board that allows up-to 4 SPARC cores to be mapped on a single board (allows up-to 16 hardware threads)
Finally, this release also supports Xilinx ISE and EDK version 10.1.
We hope this release will further enable community to build truly multi-core, multi-thread hardware platform in the configurable environment.
