Feb
14
Here's the presentation that was made on Niagara2 at ISSCC 2007, An 8-core, 64-thread, 64-bit, power efficient SPARC SoC (Niagara2)
Some basic specifications of the Niagara2 microprocessor:
[ T: OpenSPARC ]
Some basic specifications of the Niagara2 microprocessor:
- 8 SPARC cores, 8 threads/core
- 4MB L2, 8 banks, 16-way set associative
- 16KB I$ and 8KB D$ per core
- FP, Graphics, Crypto per code
- 4 dual-channel FBDIMM memory controller @ 4.8Gb/s
- X8 PCI-Express @ 2.5Gb/s
- Two 10G Ethernet port @ 3.125 Gb/s
- 342mm2
- 503 million-transistor
- fabricated on a 65nm process
- dissipates 84W when running at 1.4GHz
[ T: OpenSPARC ]
On the presentation, one slide notes that they are per lane. Another slide neglects to point this out. A pair of 10G ethernet interfaces that operate at only 3.125Gb is kinda odd since each port has a 10Gb signaling rate.
Most of it is finally explained on the slide on page 15, where we see that there is a total aggregate throughput of 921.6Gb/s for the memory, 40 for the PCI-E bus and 100 for the 10Gig-E interface. Thus, they could saturate five 10G ports if they wanted to design in the physical interfaces. The odd part is the imbalance of the memory interfaces. There are 14 "north bound" (Rx) lanes and only 10 "south bound (Tx) lanes.
Posted by John on February 14, 2007 at 07:15 PM PST #