Simply RISC creates single-core, S1, from OpenSPARC T1
Wow! Now here is an example of innovation with OpenSPARC. Simply RISC has completed the S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor. The first design released by Simply RISC is based on a cut-down version of the OpenSPARC T1 processor.
A team of former STMicroelectronics engineers in Italy and Britain has created a single-core version of Sun's 8-way, 64-bit, GPL-licensed OpenSPARC T1 processor core. Simply RISC's free, open "S1" core can run Ubuntu Linux, and targets embedded devices such as PDAs, set-top boxes, and digital cameras, the company says.
The initial 0.1 release of the S1 core is available now, and can be downloaded without registration. It requires a Linux system with bash and sed to install. For simulation, it requires Icarus Verilog (free software) or Synopsys VCS MX (commercial software). It can be synthesized using Icarus Verilog (free software) or Synopsys Design Compiler (commercial software), Simply RISC says.
Rayson
Posted by Grid on September 09, 2006 at 02:45 AM PDT #