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opensparc workshop @ NIT Trichy on March 17th
The whole workshop spans across 4-5 days and Sun will be
presenting on 17th march. The complete agenda given below will be covered in a
single day.
Prof. Kamakoti of IIT-Chennai is organizing the overall workshop
logistics with NIT-Trichy.
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Agenda for Multi-core/OpenSPARC workshop at NIT-Trichy
======================================================
Introduction
- 3-4 slides on Sun, OpenSPARC
- Introduce speakers
Chip Multithreading (Case-study "OpenSPARC T1")
- Architectural concepts
CMT basics -
Motivation
Coarse-grain vs fine-grain CMT
Design decisions (importance bandwidth, cache system, power)
- OpenSPARC T1 Micro-architecture
High level features
Pipelining and thread selection
Memory Hierarchy (LSU, L2, MCU), cache coherency/ordering
Crossbar switch
Crypto co-processor
Virtualization
Architecture Simulators for OpenSPARC T1
- Overview of SPARC Architectural Model (SAM)
- Modeling of components (Pipe, TLBs, ASIs etc)
- Modeling of Device drivers
- Tracing
- System simulation setup (Legion)
- Running OBP, Solaris, Application Traces
Porting OS on OpenSPARC
- Virtualization primer and Sun hypervisor
- Memory management with Hypervisor
- IO management with Hypervisor
- Logical Domains and Dynamic reconfiguration
- Error handling
- Boot process
Compiler and Tools for CMT
- Compiler optimizations for T1
- Parallelization options in compiler
- Parallelization for Math, Performance, Graphics libraries
- Performance analysis and Optimization tools
Analyze, DRDT, BIT, SPOT
- GCC support
- System Tuning and Troubleshooting (ATS)
- Unified Solaris Binary (mkusb/ckusb)
Closing comments
- What is next (e.g. FPGA support)
- How to participate (Forums, website etc)
Posted at 08:10AM Mar 07, 2007 by G S Hiregoudar in India Edu |