Charlie Chen's Weblog
Thursday Nov 29, 2007
How does MSI/MSI-X work - MSI part?
1. Background
MSI, Message Signaled Interrupts, uses in-band pci memory space message to raise interrupt, instead of conventional out-band pci INTx pin.
When system wants to use msi, it should setup msi pci capability control registers. Simply said, it would write address register (32b or 64b) and data register, and set enable bit of msi control register. When device chip wants to send interrupt, it will write the data in data register to the address specified in address register.
MSI-X is an extension to MSI, for supporting more vectors. MSI can support at most 32 vectorsm while MSI-X can up to 2048.
Using msi can lower interrupt latency, by giving every kind of interrupt its own vector/handler. When kernel see the message, it will directly vector to the interrupt service routine associated with the address/data. The address/data (vector) were allocated by system, while driver needs to register handler with the vector.
By allocate vector area generally for all kinds of pci devices, system will reach a general solution to reporting interrupts quickly.
2. Msi registers
capability id: 1b, val = 0x5, the code of this capability.
next pointer: 8b, the offset of the next capability, 0 if this is the last one.
bit 8: if per-vector masking is supported
bit 7: if 64b address is used
bits 6-4: number of allocated vectors by system, evaluated by 2 to this 3-bit value.
bits 3-1: number of requested vectors by function, evaluated by 2 to this 3-bit value.
bit 0: if msi is enabled, disabled by default, driver can't use this bit to mask interrupt
message address: 32b
message upper address: 32b, only used when 64bit address is enabled by bit 7 of control register
message data: 16b, specified by system, lower bits combination can be modified reflecting the identity of the interrupt source.
pending bits: 32b
Every vector is given a number, corresponding to a bit in mask and pending resgister. Mask bit set indicates that the function is prohibited from sending the associated message. The pending bit set has s pending associated message. This mechanism enable software to disable or defer message sending on a per-vector basis.
Posted at 01:02AM Nov 29, 2007 by gnunu in General | Comments[2]
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comments on, said nunu.
Posted by nunu on November 30, 2007 at 01:08 AM PST #
Oh~~my God... Add comments successfully:)
Posted by firewave on December 05, 2007 at 11:45 PM PST #