Charlie Chen's Weblog

To simulate an Ethernet controller, we need to:

Registers access on a chip are just like RAM's operation, with one exception that registers' read/write operation has side effects such as causing packet to send, or read clear, while RAM is totally a passive part. It's just the side effects that is the key to simulate an IO module's logic, no matter what kind of and complex the module - scsi controller, simple UART, or NIC.

Important as the correct logic of registers' interpretation, so is to make the asynchronous way up from IO to cpu expectable. This is not like the real world, and the difference is very important for a simulator. In real world, there are two ways of communication between modules including cpu, memory, various IO modules. They are synchronous way and asynchronous way.

In simulator, we need to take care of asynchronous way in a semi-deterministic way: at least we should guarantee an asynchronous event can happen timely, or, not to be delayed too much to change upper layer application's behavior drastically.

The method is to timing all the events happened from IO land. Simulator must have implemented some form of central clock. The task here is to relate the IO events to this central clock.

The result is change asynchronous events to synchronous ones. The essential is that all events in a simulator should be timed. How to do that smartly is difficult.