Tuesday August 15, 2006 The eco-responsbile rebate offer has been written up at eWeek.com with an excellent interview of Joyent's experience with energy savings and at SearchDataCenter.com.
Last week marked my first opportunity to do performance testing on T2000's. Its remarkable to see the single UltraSparc T1 chip present itself as a 32-way SMP to Solaris.
CPU CPU
Location CPU Freq Implementation Mask
------------ ----- -------- ------------------- -----
MB/CMP0/P0 0 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P1 1 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P2 2 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P3 3 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P4 4 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P5 5 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P6 6 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P7 7 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P8 8 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P9 9 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P10 10 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P11 11 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P12 12 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P13 13 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P14 14 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P15 15 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P16 16 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P17 17 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P18 18 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P19 19 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P20 20 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P21 21 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P22 22 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P23 23 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P24 24 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P25 25 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P26 26 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P27 27 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P28 28 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P29 29 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P30 30 1200 MHz SUNW,UltraSPARC-T1
MB/CMP0/P31 31 1200 MHz SUNW,UltraSPARC-T1
(2006-08-15 11:20:33.0)
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Friday December 09, 2005 Well the Niagara was launched in volume this week as the Sun Fire T2000. I can only assume someone at Sun has put a T2000 in his hands. If not, Luiz, you can try one risk free for 60 days. I'm looking forward to his next paper titled, "Sun's UltraSPARC T1 CMP architecture solves Google's energy woes."
(2005-12-09 10:44:18.0)
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Tuesday December 06, 2005 
I was really impressed during the webcast with an infrared image of a state of the art processor VS the UltraSPARC T1. The differential of heat across the various portions of the state of the art chip was 50 degrees celsius. The UltraSPARC T1 was a fairly uniform temperature at the cool end of the thermal spectrum in the image.
I love cool computers that are quiet. I hope the CMT revolution will trickle down to desktop processors soon. I have always owned Macs at home, which have always been quieter than PC's as they were based on cooler PowerPC processors. However, dissapointingly my latest Mac, the iMac G5, has a fan that spins up under higher loads. (2005-12-06 20:00:30.0)
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eBay loves it, Oracle adjusts licenses for it, PG&E rebates it, and more...
"It" is the UltraSPARC T1 (formerly Niagara) of course. The webcast of today's launch is packed with information not in the press releases. Here are my highlights.
eBay
Heather Peck, manager of the marketplace environment at eBay, who is responsible for the eBay's 6000-8000 servers was present at the launch event. eBay was the first customer to get a sneak peak at a T2000. Heather stated that they are done with building out new data centers every time they max out the space and power. She is an engineer by trade and as such she hasn't been excited about computer hardware developments in a number of years, but the T2000 has her and her team excited by opening their eyes to new possibilities due to its performance VS space/power economics. This is THE news I was looking for today.
Oracle
Oracle will sell licenses for the UltraSPARC T1 at 0.25 per core, which means an 8 core T1 will be licensed as a 2 CPU machine. An Oracle engineer said the first look at their in house performance test "pinned his ears back".
Pacific Gas & Electric
PG&E is going to be offering a rebate program for people who deploy UltraSPARC T1 systems. That is a surprise announcement to me. That means we really got the eco-responsibility message out there.
Electronic Data Systems
An EDS representative reported that they took out 48 rack units and replaced with 4 rack units of Ultrasparc T1 systems and cut the power from 5000 watts to 800.
Sun Sim Datacenter
Sun has developed a configurator to enable customers to simulate their workloads along with the space, power and cooling consumption in order to compare the reduction in monthly spend when replacing their systems with UltraSPARC T1 servers. You can learn about and download the Sim Datacenter here.
(2005-12-06 12:25:24.0)
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Thursday December 01, 2005
Twenty-three days left in the Christmas advent calendar. Five days left in the advent of Sun's next generation UltraSparc systems. For other's of you eagerly awaiting the arrival of energy, space and cost efficient computing, Sun is providing a Konfabulator countdown widget.
(2005-12-01 10:57:31.0) Permalink Comments [1]
Monday November 14, 2005 For my value add, I'd like to create a car anology to help demystify the breakthrough performance and efficiency of the T1. I'm no chip guy, just a software geek, but I think I've got the big picture concepts.
In this analogy, a car traveling over a distance is equal to getting work done with a computer. In contemporary chips like the Xeon, engine speed has been optimized to create a really fast car. In this analogy, the Xeon car is always rev'd up to 3,000 rpm's (3000 Megahertz, or 3 Ghz). As in the real world, it takes significant juice to stay rev'd at 3000 rpm's, gas or watts its relatively similar. Like a car engine's rpm's, transistors have an efficiency curve. At lower megahertz there is less current leakage, just as there is a range in the rpm's where fuel is optimally converted to horsepower. The T1 engine is in a sweetspot at 1200 megahertz.
Now you might be thinking, "This sounds boring, is the T1 just a throttled engine that can't possibly compete with the race engine Xeon? Where is the fun in that?".
Here's the kicker where the T1 changes the game. Just as there are stop lights in the world of automobiles, so too in the CPU world. Those stop lights are called cache misses, where the CPU has to wait for data to be fetched from RAM. The Xeon sits at the stop light cache miss rev'd up at 3000 rpm waiting to jackrabbit off the line as soon as that data arrives (green light). The T1 plays by different rules. Whenever is comes to a stop light, it sees not one signal, but an array of 32. As long as 1 of the 32 stop lights is green, the T1 keeps on moving. And remember in this analogy, movement equals getting work done. It is because the T1 has 8 cores with 4 threads each that it always has 32 independent jobs looking for data. Therefore it rarely, if ever, encounters 32 red lights causing a full stop. There are typically dozens of green lights greeting it at every stop light.
For the official explanation of how the T1's 32 threads best a rev'd up Xeon, see the Throughput Whitepaper. (2005-11-14 10:06:18.0)
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