mellanox InfiniScale IV architecture
Mellanox announced InfiniScale IV architecture in sc2007
the benefits are:
- 40Gb/s server and storage interconnect (4x QDR)
- 120Gb/s switch-to-switch interconnect (12x QDR)
- 60 nanosecond switch hop latency
- 36-port switch devices for optimal scalability
- Adaptive Routing to optimize data traffic flow
- Congestion control to avoid hot spot
Using 36 port silicon to build an non-blocking CLOS switches, in 3 layers setup, one can get(for 24 port chipset we can get 288 port in 3 stages):
- 72 ports: 6 chips, 9 links between chips, 2 cores and 4 leafs
- 108 ports: 9 chips, 6 links between chips, 3 cores and 6 leafs
- 216 ports: 18 chips, 3 links between chips, 6 cores and 12 leafs
- 324 ports: 27 chips, 2 links between chips, 9 cores and 18 leafs
- 648 ports: 54 chips, 1 link between chips, 18 cores and 36 leafs
For 5 stage non-blocking CLOS network one can get (24 port chipset we can get to 3456 port in 5 stages)
- 2 x 648 = 1296 port
- 3 x 648 = 1944 port
- 4 x 648 = 2592 port
- 6 x 648 = 3888 port
- 9x 648 = 5832 port
- 12 x 648 = 7776 port
- 18x 648 = 11664 port
as comparison with InfiniScale IV we list the InfiniScale III 24 port features here:
- Twenty-four 10 or 20Gb/s Infiniband 4X ports or eight 30 or 60Gb/s Infiniband 12X ports (or any combination)
- 480Gb/s (SDR version) or 960Gb/s (DDR version) of total switching bandwidt
- Scalable to thousands of Ports
- 96 integrated 2.5Gb/s (SDR version) or 5Gb/s (DDR version) SerDes interfaces (physical layer)
- Auto-negotiation of port link speed
- Ultra low latency cut-through switching (less than 200 nanoseconds) MTU Size from 256 to 2K bytes
- Supports Multi-Protocol Applications for Clustering, Communication, and Storage
- Integrated Subnet Management Agent (SMA)
Posted at
05:38PM Apr 27, 2008
by hstsao in HPTC |