Early Access Program: T5120/T5220 Alpha Testing

Here's a view of the chip that beats at the heart of every T5120/T5220. I created this illustration soon after "tapeout" (that's basically the event the data is sent for fabrication after the design of the chip has finished). It went into a variety of presentations like the one given at the Hot Chips conference in 2007.

The eight cores (SPC) in the middle of the chip are interconnected through the crossbar (CCX). Each core includes its own floating point unit and crypto unit. The blocks for the 4MB level 2 data cache (L2D) are placed near the left and right edges of the chip. Near the lower right corner is the network interface (RDP, TDS, RTX, MAC), supporting two 10Gb Ethernet ports. The four FB-DIMM memory controllers (MCU) are located near the left and right input/output interfaces (FSR and PSR). Near the lower left corner is the PCI-E port (PEU).