Robin McDonald's Weblog
ERP Big Picture
Archives
« February 2006 »
SunMonTueWedThuFriSat
   
1
2
3
4
5
6
11
12
13
15
18
19
20
21
22
23
24
25
26
27
28
    
       
Today
XML
Search

Links
 

Today's Page Hits: 47

« Previous day (Feb 9, 2006) | Main | Next day (Feb 11, 2006) »
20060210 Friday February 10, 2006
"Putting a large number of these medium-sized cores on a chip is not optimal." - FUD

This comment came from a blog I'm not sure if it was deliberate FUD or the author was just not aware that in today's world the old rules of thumb are no longer relevant.

Today almost all business applications are either multi-threaded or multi-process [firefox, apache, oracle, mysql, postgress, java, ...] So you are more interested in the performance of many threads than a single thread. The old thinking is cache misses are bad do anything to reduce cache misses build a bigger cache, keep other cores away from this cache because when we have a cache miss the processor will stall and that will reduce performance. The real problem is not cache misses but processor stalls. The T1 has 4 hardware threads per core so when we have a cache miss it can work on another thread, the processor doesn't stall. So does the T1 have more cache misses than other processors – maybe, does it reduce the performance of the T1 – No. More theory here more practice here.



[ T: NiagaraCMT CoolThreads CPU ]


Feb 10 2006, 10:39:42 AM PST Permalink Comments [2]