Tilera has announced availability of the TILE64, a chip with 64 cores (tiles) interconnected by a mesh-like on-chip network. Targeted at advanced networking and multimedia processing, the chip features 64 tiles each with a 3 VLIW pipeline processor, L1 and L2 caches, as well as a non-blocking switch that meshes the tile with the others on the chip. The chip provides the option of running an independent OS on each tile or an OS spanning multiple tiles.

A c|net News article has more details on the chip. The Tilera website also has an architecture brief.

Dr. Agarwal, CTO and co-founder of Tilera, has earlier worked on the MIPS processor used notably by SGI, and is leading the RAW project at the Computer Science and Artificial Intelligence Laboratory, MIT.

Tags : multicore embedded cpu tilera