The Navel of Narcissus
Josh Simons' Coordinates in the Blogosphere

20070625 Monday June 25, 2007

HPC Consortium: Niagara 2 Processor

Barton Fiske, one of Sun's Technical Marketing Specialists, and Ruud van de Pas, Sun Senior Staff Engineer, gave back-to-back talks today at the HPC Consortium meeting in Dresden about Sun's upcoming Niagara 2 processor and its applicability to High Performance Computing.

You may recall that the current Niagara processor (officially called the UltraSPARC T1) has but a single floating-point unit across all eight cores and 32 threads. Hardly a compute engine for the vast majority of HPC workloads, though of interest perhaps to some customers in the intelligence community and in certain segments of life sciences where integer operations are important. By contrast, the N2 processor has eight floating-point units--one per core. However, N2 inherits its overall philosophical approach from the UltraSPARC T1 in that its cores are relatively simple (no superscalar, no out of order execution, etc), concentrating instead on delivering a significant degree of chip multithreading (CMT) with 8 cores and 64 threads per N2 die. Our HPC customers are wondering whether N2-based systems will be useful for HPC workloads.

Barton lead with a description of the N2 processor and a detailed look at the various systems in which Niagara 2 will be used from small systems to those using Victoria Falls. Ruud then followed with a description of some of the benchmarking work he has been doing on early N2 systems, looking at how a variety of HPC applications (primarily C and Fortran codes) perform. His results were very preliminary and since both his talk and Barton's were given under non-disclosure at the Consortium meeting, I cannot share detailed results here. However, I will say that the combination of increased floating point capabilities, a better floating point implementation, and high off-chip bandwidth makes our next generation Niagara-based systems worthy of consideration for some HPC workloads. Sorry to be vague for now, but we will have much more information to share once we start shipping N2-based systems.


(2007-06-25 11:18:02.0) Permalink Comments [0]

HPC Consortium: Sun Labs Perspectives

Hans Eberle presented a Sun Labs perspective on High Performance Computing at the HPC Consortium meeting in Dresden today. He gave overviews of a few of the current projects running in Sun Labs that are relevant to HPC, including proximity interconnect and Fortress. For a complete list of Sun Labs project, visit the Sun Labs project page.

Both proximity interconnect and Fortress were explored by Sun as part of the DARPA HPCS project and we continue to invest in both efforts even though we have completed our work under Phase II of that project.

Fortress has been designed specifically as a language for expressing scientific applications. Its design principles included support for a mathematical notation, growability, safety, and implicit parallelism. Here is an example of Fortress code formatted using a set of Emacs macros supplied with Fortress:


[fortress sample code]

While the above may look strange to the average programmer, think how strange C or Fortran code looks to a scientist trying to solve a complex set of equations in their domain of expertise. Or actually, meditate on the fact that we as an industry have beaten these poor scientists into submission and forced them to express their problems in something so foreign to them as current programming languages. A bug perhaps?

Unlike most languages that begin as serial languages and then add features or annotations to express parallelism, Fortress was designed specifically with parallelism built in as is illustrated on the slide below.


[fortress parallelism]

A Fortress interpreter has been released under open source and an open source community has been established to further develop the code. The web site is here. If you are interested, the Fortress language specification can be found here.


(2007-06-25 10:25:32.0) Permalink Comments [0]

HPC Consortium: Blackbox

[blackbox in dresden]

We have a Blackbox here in Dresden (shown above) and it has been a popular tour for the Sun customers and partners attending the Sun HPC Consortium meeting. We also had a talk about Project Blackbox, delivered by Robert Zwickenpflug of Sun Microsystems GmbH. For those not familiar, Blackbox is a datacenter in a box--specifically, a datacenter built into a standard 20' shipping container.

Robert reviewed the Blackbox specs--that it supports up to 266 rack units of equipment in a total of eight 19" racks in about 160 square feet. Depending on the CPU used, one could fit 500 CPUs or 2000 cores or 8000 threads in a single Blackbox container or perhaps 1.5 petabytes of storage. A Blackbox system can handle about 200 kW of power and cooling due to its innovative water-cooled design. Both Sun and 3rd party components may be installed.

We figure a Blackbox can be deployed in 1/10 the time of a traditional datacenter (conservatively), that it is about 20% more energy efficient than an AC-cooled datacenter, and that one could save perhaps $150K per year by locating a Blackbox close to low-cost power sources (possible due to its mobile nature and based on estimated energy costs of $0.25/kWh in an urban environment versus a $0.03/kWh rural rate.)


(2007-06-25 09:57:54.0) Permalink Comments [0]

HPC Consortium: Andy Bechtolsheim


[andy bechtolsheim]

Andy spoke today at the HPC Consortium meeting in Dresden about the five key challenges to building petascale (as in 10^15 floating-point operations per second) computer systems. They are: scaling application performance, keeping the bandwidth-to-FLOPs ratio balanced in the system, scaling the interconnect fabric, power efficiency and cooling, and reliability to support capability applications.

He went on to describe in detail how Sun will build petascale computers using a concept that will be officially previewed at ISC in Dresden tomorrow. He talked about network topologies, mechanical issues, power, cooling, and compute density, and then showed how our technologies will be used to build the 500+ TFLOP Ranger system to be installed later this year at the Texas Advanced Computing Center (TACC) and other sites which have not yet been disclosed.

More details and perhaps some photos tomorrow after the announcement.

(2007-06-25 09:38:35.0) Permalink Comments [1]


 
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