Monday June 25, 2007 | The Navel of Narcissus Josh Simons' Coordinates in the Blogosphere |
|
HPC Consortium: Niagara 2 Processor Barton Fiske, one of Sun's Technical Marketing Specialists, and Ruud van de Pas, Sun Senior Staff Engineer, gave back-to-back talks today at the HPC Consortium meeting in Dresden about Sun's upcoming Niagara 2 processor and its applicability to High Performance Computing. You may recall that the current Niagara processor (officially called the UltraSPARC T1) has but a single floating-point unit across all eight cores and 32 threads. Hardly a compute engine for the vast majority of HPC workloads, though of interest perhaps to some customers in the intelligence community and in certain segments of life sciences where integer operations are important. By contrast, the N2 processor has eight floating-point units--one per core. However, N2 inherits its overall philosophical approach from the UltraSPARC T1 in that its cores are relatively simple (no superscalar, no out of order execution, etc), concentrating instead on delivering a significant degree of chip multithreading (CMT) with 8 cores and 64 threads per N2 die. Our HPC customers are wondering whether N2-based systems will be useful for HPC workloads. Barton lead with a description of the N2 processor and a detailed look at the various systems in which Niagara 2 will be used from small systems to those using Victoria Falls. Ruud then followed with a description of some of the benchmarking work he has been doing on early N2 systems, looking at how a variety of HPC applications (primarily C and Fortran codes) perform. His results were very preliminary and since both his talk and Barton's were given under non-disclosure at the Consortium meeting, I cannot share detailed results here. However, I will say that the combination of increased floating point capabilities, a better floating point implementation, and high off-chip bandwidth makes our next generation Niagara-based systems worthy of consideration for some HPC workloads. Sorry to be vague for now, but we will have much more information to share once we start shipping N2-based systems. (2007-06-25 11:18:02.0) Permalink Comments [0]
Trackback URL: http://blogs.sun.com/simons/entry/hpc_consortium_niagara_2_processor
Comments:
Post a Comment: |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||