Many-core Mania

A new start

Friday Jan 29, 2010

A new start at Oracle. 

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Posted at 03:29PM Jan 29, 2010 by skrish in Personal
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404-ed

Thursday Jun 21, 2007

my blog is not working. this is a test!

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Posted at 01:30PM Jun 21, 2007 by skrish in Personal
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Heard at DAC

Friday Jun 15, 2007

I heard someone mentioning at DAC last week that the amount of electronics in a BMW (microchips et al.) would draw significant electric power from the battery/engine resulting in lowering gas efficiency, if not for low-power design of those chips. I found this interesting since this would be the one of the last places where one would expect the need for low-power chips that are normally indispenable for handheld devices (cellphones, laptops,etc.)

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Posted at 10:58AM Jun 15, 2007 by skrish in Sun
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DAC-44 notes

Friday Jun 15, 2007

I was at the DAC (Design Automation Conf.), the biggest trade conference in the EDA industry held at San Diego last week. Presented a paper from my PhD research work (shameless plug to my dissertation summary). Overall it was a very exciting conference. Here are some of the notes I made from the sessions I sat in during DAC last week.

Tuesday: 06/05


  1. Panel Session: Mega Trends and EDA 2017

    1. Moore's law will continue for next 10 yrs; corollary is
      the law for manycore processors (might see 500+).
    2. EDA/semicon industry for next 10 yrs will be at 8%
      (single digit) growth; Not the era of 14-15% growth of
      90's.
    3. Industry in "golden age" after initial stage of
      irruption, tech bubble, etc.
    4. More interaction/convergence b/w foundries and EDA tools
      companies
    5. Power, DFM, DFY major issues, but not show-stoppers;
      consensus that solutions will be found.
    6. Application driver may not be consumer electronics but
      healthcare, auto, etc. (Juan Antonio Cabarallo, Aragon
      Venture)
    7. Convergence of design platforms; consolidation across
      semicon and EDA companies (Cabarallo)
    8. Will see emergence of more application software
      development (perf. optimizers, tuners, etc) by EDA
      companies (Prof. Kurt Keutzer, Berkeley)
    9. Techeconomics will drive the respective industries (Aart
      de Gaeus, Synopsys)

  2. 2. Paper session: Leakage Power Analysis and Optimization

    1. Paper #3: modeled dependence of Vt on width, useful in
      the context of wider transistors.

  3. 3. Panel session: Early power-aware design and validation, myth or
    reality

    1. Consensus that it is largely a reality as several
      designs use it successfully
    2. No consensus on what accuracy can/will be achieved
    3. Data quality bad in arch.-level power but early
      power-aware design does help and works in real design.
      Start with the following: i. Arch. performance model ii. Block-level activity from simulator, iii. Switching cap extrapolate from previous generation design
    4. Silicon within 10% arch. estimates obtained with
      intensive high-level modeling effort (Steve Curtis,
      Intel)
    5. High-level power estimation/opt tools confined to
      startups; big EDA companies not betting on it since not
      sure when system-level design will take off (E. Macii,
      Univ. Torino)
    6. Lack of standard format for exchanging power info;
      Accellera UPF expected to make things better
    7. Limited availability of info. for characterizing power
      models because knowledge of the IP is needed (companies
      not ready to share)


Wednesday: 06/06

  1. Paper session: Process-aware physical design

    1. Paper #1: proposes buffer insertion under process
      variations. First, do slew-constrained buffering, then
      iteratively check timing and do delay-constrained
      buffering until timing is satisfied.


Thursday: 06/07

  1. Special Session: Thousand core chips

    1. Shekar Borkar, Intel:

      1. 45nm can integrate 8 bil transistors; 2014 we
        will hit terascale (100 bil); integration
        capability will facilitate 1K cores in 10 yrs
      2. transistors moving to trigate; delay and energy
        scaling will slow down; 1.25x realistic freq.
        scaling; 0.7x vdd scaling; 1000 core chips will
        have 1000w of power
      3. Pollacks rule: in single core, 2x (power or
        area) = 1.4x perf.
      4. multi-core chips will have general purpose,
        special purpose procs and connected by
        interconnect fabric; opportunity for
        fine-grained pwr. mgmt. in multicore; parallel
        s/w key to multicore success.
      5. Having many small cores will give better
        performance but parallelism in applications
        should double every generation to break even;
        means that s/w shd be able to parallelize better
      6. How to feed the beast? 100GBps BW may be needed.
        I/O power at this rate will be 25W using ~400
        differential pins. Reduce distance between cores
        to abt. 1-2mm; 3d chips with DRAM on bottom
        probably best solution.
      7. Resilient uarch in manycore needed because
        components will get more and more unreliable
        (soft errors, variability, aging, etc.);
        possible solutions: dynamic on-chip testing,
        redundancy, etc.

    2. Anant Agarwal, MIT:

      1. KILL rule for multicore (Kill if less than
        linear): A resource in a core (power or area)
        must be inc. in area only if the core's perf.
        improvement is more than the inc. in the
        resource.

    3. Wen-Mei Hwu, UIUC:

      1. Parallel prog models needed for >4 cores. Models
        should last for many generations of multicore.

      3. Implicitly parallel prog implies APIs managing
        parallelism. Explicitly parallel prog implies
        programmers managing parallelism. In former,
        algorithm should be parallel but can be written
        in seq. language. Latter is rigid (need to
        change as # of cores multiply) and not
        advisable.

    4. 4. John Deringer, IBM (EDA for Multi-core):

      1. Growing use of diverse modular design
      2. EDA challenges: custom design efficiency,
        ASIC-style productivity, design and verification


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Posted at 10:19AM Jun 15, 2007 by skrish in Sun
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Kick-off entry and a short primer on Manycore

Wednesday Jun 13, 2007

Kicking off the shiny new Sun blog. I liked this theme for its green color (Go Green!! Go White). The title (Manycore Mania) represents, in my view, the architectural driver of the near-future silicon/EDA industry. Just how may cores can/will we go? Will we see a Moore's law corollary for core explosion? So why manycore from single-core architectures? one word: POWER. With increasing clock frequencies, it was no longer viable to obtain perf. improvements without precipitously pushing the power dissipation higher. Things started to run into a wall when increasing power led to hotter chips, unmanageable leakage, thermal breakdown, decreasing reliability, failure rates, etc. This reminds me of what I heard in HPCA-11 a few years ago: "Pipelining was the last great innovation in computer architecture" (I don't recall who said it but I promise to find out soon). Beyond a certain limit, deeper pipelines, issue widths, superscalarity, higher clock freq., etc., were not yielding desired RoI. So the industry switched to multicore and we obtained overall power reduction by using slower clocks and simpler cores and sacrificing per-core performance but gaining in overall throughput due to parallel execution. From thereon, we have evolved to manycore.

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Posted at 09:53AM Jun 13, 2007 by skrish in Sun
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