Years ago, 8259 was extensively adopted by single CPU PC and the IRQ and vector number was clear to OS.  Now, we have APICs in Intel multiple processor systems.  It is quite confusing how the IRQ numbers are assigned to OS.  Here is the output of "::interrupts" output in mdb.


 ::interrupts

IRQ  Vect IPL Bus    Trg Type   CPU Share APIC/INT# ISR(s)

4    0xb0 12  ISA    Edg Fixed  3   1     0x0/0x4   asyintr

9    0x81 9   PCI    Lvl Fixed  1   1     0x0/0x9   acpi_wrapper_isr

14   0x41 5   ISA    Edg Fixed  7   1     0x0/0xe   ata_intr

20   0x20 1   PCI    Lvl Fixed  4   1     0x0/0x14  ehci_intr

21   0x21 1   PCI    Lvl Fixed  5   1     0x0/0x15  ohci_intr

48   0x60 6   PCI    Lvl Fixed  6   1     0x1/0x0   e1000g_intr  <--- first pin of second IOAPIC

49   0x61 6   PCI    Lvl Fixed  6   1     0x1/0x1   e1000g_intr

50   0x62 6   PCI    Lvl Fixed  6   1     0x1/0x2   e1000g_intr

51   0x63 6   PCI    Lvl Fixed  6   1     0x1/0x3   e1000g_intr

63   0x40 5   PCI    Edg MSI    2   1     -         mpt_intr


....


We have IRQ numbers from 4 to 63 here.  But how they are assigned?  Before we understand it, we should firstly look into IOAPIC.  Usually, Intel IOAPIC have 24 interrupt pins.  The interrupt pins of PCI devices will be routed to these pins hierarchically.  And the routing paths are almost harden into the motherboard, though PCI devices may have two selectable pins for some flexibility.  The first interrupt input pin of first IOAPIC will be assigned IRQ 0, while  the forth pin will be assigned IRQ4 in this example, and so on.  If the system have two more IOAPICs, the first IRQ number will start from the multiples of 24, 48 in the example above.  Now, we know the IRQ numbers are from the input pins of IOAPICs.  IRQ numbers are not necessary bundled with the vector numbers in APICs, because the vector numbers can be re-programmable. To some degrees, IRQ numbers are the hardware level layout of interrupt lines and vector numbers are in software level and more meaningful to OS.
  As to the MSI interrupt, IOAPIC is no longer required to deliver the interrupt.  For, MSI message can target the host bridge address as other IO transactions. So such format will be printed for MSI devices:


24   0x61 6   PCIe   Edg MSI    0   1     -    e1000g`e1000g_intr_pciexpress
^
|-------- no ioapic listed



Comments:

Post a Comment:
  • HTML Syntax: NOT allowed

This blog copyright 2009 by Ming Shu