UltraSPARC T2 Crypto performance
Detailed breakdown of the peak performance we can expect from the UltraSPARC T2 cryptographic accelerators.
Bulk Cipher
|
Algorithm |
Bytes/cycle/SPU |
Gb/s/chip @ 1.4GHz |
|
RC4 |
1 |
83 |
|
DES |
1 |
83 |
|
3DES |
0.33 |
27 |
|
AES-128 |
0.53 |
44 |
|
AES-192 |
0.44 |
36 |
|
AES-256 |
0.38 |
31 |
[N.B. common modes of operation supported]
Secure Hash
|
Algorithm |
Bytes/cycle/SPU |
Gb/s/chip @ 1.4GHz |
|
MD5 |
0.5 |
41 |
|
SHA-1 |
0.4 |
32 |
|
SHA-256 |
0.5 |
41 |
Public-key
|
Algorithm |
Ops/cycle/SPU |
Ops/s/chip @ 1.4GHz |
|
RSA-1024 |
4625 |
37000 |
|
RSA-2048 |
800 |
6400 |
|
ECCp-160 |
6540 |
52300 |
|
ECCb-163 |
11500 |
92100 |
Out of curiosity, how did you measure these values?
Posted by Derek Morr on August 11, 2007 at 08:00 AM PDT #
And how that compares with Via C7 AES etc performance? Just curious.
Posted by Igor on August 13, 2007 at 01:55 PM PDT #